1. Field of the Invention
The present invention relates to a memory testing apparatus for testing various kinds of semiconductor memories including a memory being constructed by, for example, a semiconductor integrated circuit (hereinafter, referred to as IC) and a method of analyzing a relief or repair of failure cell or cells in a memory, which includes the steps of counting the number of failure memory cells of a semiconductor memory tested by this memory testing apparatus and determining whether or not a repair of the tested semiconductor memory is possible. (Hereinafter, a memory being constructed by a semiconductor integrated circuit is referred to as IC memory.) More particularly, the present invention relates to a method of analyzing a repair of failure cell or cells in a memory, which includes the step of specifying an address of a failure memory cell in a memory of redundancy structure in a short time and a memory testing apparatus having a failure relief analyzer using this analyzing method.
2. Description of the Related Art
Recently, an IC memory is being increased in its memory capacity and miniaturized in its size, and accompanied therewith, a defect rate in IC memories have been increased. In order to decrease the defect rate, in other words, in order to prevent the yield of IC memories from being lowered, there are manufactured IC memories in each of which, for example, one or more failure memory cells can be electrically replaced by a substitute or alternative memory cell (also called a spare line, relief line or redundancy circuit in this technical field). The IC memories of this kind each having substitute or alternative memory cells (hereinafter referred to as spare line) is called a memory of redundancy structure in this technical field, and a decision as to whether the redundancy-structured memory can be relieved or not is rendered by a failure relief analyzer.
FIG. 5 is a block diagram showing, in outline, a configuration of the general memory testing apparatus having a failure relief analyzer, which has conventionally been used. This memory testing apparatus TES comprises, roughly speaking, a main controller 111, a pattern generator 112, a timing generator 113, a waveform formatter 114, a logical comparator 115, a driver 116, an analog level comparator (hereinafter referred to as comparator) 117, a failure analysis memory 118, a failure relief analyzer 120, a logical amplitude reference voltage source 121, a comparison reference voltage source 122 and a device power source 123. Further, in the following description, a case that the memory testing apparatus will test IC memories will be described. In case of testing various kinds of semiconductor memories other than IC memories by the memory testing apparatus, however, they will be tested in similar manner.
The main controller 111 is generally constituted by a computer system, in which a test program PM created by a user (programmer) is stored in advance, and the entire memory testing apparatus is controlled in accordance with the test program PM. The main controller 111 is connected, via a tester bus BUS, to the pattern generator 112, the timing generator 113, the failure analysis memory 118, the failure relief analyzer 120 and the like. Although not shown, the logical amplitude reference voltage source 121, the comparison reference voltage source 122, and the device power source 123 are also connected to the main controller 111.
An IC memory to be tested (IC memory under test, generally called MUT) 119 is mounted on a IC socket of a test head (not shown) constructed separately from the memory testing apparatus proper. Usually, a member called a performance board is mounted on the upper portion of the test head, and a predetermined number of IC sockets are mounted on the performance board. Accordingly, the IC memory under test 119 is mounted on associated one of the IC sockets. In addition, a printed board called pin card in this technical field is accommodated inside the test head. Usually, a circuit including the driver 116 and the comparator 117 of the memory testing apparatus TES is formed on this pin card. In general, the test head is mounted on a test section of an IC transporting and handling apparatus called handler in this technical field, and is electrically connected to the memory testing apparatus proper by signal transmission means such as a cable, an optical fiber or the like.
First of all, before the test of an IC memory is started, various kinds of data are set by the main controller 111. After the various kinds of data have been set, the test of the IC memory is started. When the main controller 111 gives a test starting instruction or command to the pattern generator 112, the pattern generator 112 starts to generate a pattern. The pattern generator 112 supplies test pattern data to the waveform formatter 114 in accordance with the test program PM. On the other hand, the timing generator 113 generates a timing signal (clock pulses) for controlling operation timings of the waveform formatter 114, the logical comparator 115 and the like.
The waveform formatter 114 converts the test pattern data supplied from the pattern generator 112 into a test pattern signal having a real waveform. This test pattern signal is applied to the IC memory under test (hereinafter referred to as memory under test) 119 via the driver 116 that amplifies the voltage of the test pattern signal to a waveform having an amplitude value set by the logical amplitude reference voltage source 121. The test pattern signal is stored in a memory cell of the memory under test 119 having an address specified by an address signal, and the storage content is read out therefrom in a read cycle executed later.
A response signal read out from the memory under test 119 is compared with a reference voltage supplied from the comparison reference voltage source 122 in the comparator 117, and it is determined whether or not the response signal has a predetermined logical level, i.e., whether or not the response signal has a predetermined logical H (logical high) voltage or logical L (logical low) voltage. A response signal determined to have the predetermined logical level is sent to the logical comparator 115, where the response signal is compared with an expected value pattern signal outputted from the pattern generator 112, and whether or not the memory under test 119 has outputted a normal response signal is determined.
If the response signal does not coincide with the expected value pattern signal, the logical comparator 115 determines that the memory cell having an address of the memory under test 119 from which the response signal has been read out is defective (failure), and generates a failure signal indicating that fact. Usually, when the failure signal is generated, a writing of a failure data (generally logical xe2x80x9c1xe2x80x9d signal) in the failure analysis memory 118 applied to a data input terminal thereof is enabled, and the failure data is stored in an address of the failure analysis memory 118 specified by an address signal being supplied to the failure analysis memory 118 at that time.
The failure analysis memory 118 has its operating rate or speed and its memory capacity equivalent to those of the memory under test 119, and the same address signal as the address signal applied to the memory under test 119 is also applied to this failure analysis memory 118. In addition, the failure analysis memory 118 is initialized prior to the start of a testing. For example, when initialized, the failure analysis memory 118 has data of logical xe2x80x9c0sxe2x80x9d written in all of the addresses thereof. Every time a failure signal indicating that the anti-coincidence is generated from the logical comparator 115 during a testing of the memory under test 119, a failure data of logical xe2x80x9c1xe2x80x9d indicating the failure of a memory cell is written in the same address of the failure analysis memory 118 as that of the memory cell of the memory under test 119 from which that anti-coincidence has occurred.
In general, this logical xe2x80x9c1xe2x80x9d signal is stored in the same address of the failure analysis memory 118 as that of the failure memory cell of the memory under test MUT.
On the contrary, when the response signal coincides with the expected value pattern signal, the logical comparator 115 determines that the memory cell having an address of the memory under test 119 from which the response signal has been read out is not defective (pass), and generates a pass signal indicating that fact. Usually, this pass signal is not stored in the failure analysis memory 118.
After the testing has been completed, the failure data stored in the failure analysis memory 118 are read out therefrom into the failure relief analyzer 120, and it is determined whether a relief or repair of failure memory cells of the tested IC memory 119 is possible or not.
The failure relief analyzer 120 separately and simultaneously counts the total number of failure memory cells stored in the failure analysis memory 118, and the number of failure memory cells on each address line of row (lateral) address lines and column (longitudinal) address lines stored in the failure analysis memory 118, and analyzes to determine whether the relief of the tested memory can be done or not by use of spare lines provided on each of a plurality of storage areas (memory cell array) of the memory under test 119.
Further, in FIG. 5, the block diagram is depicted such that the test pattern signal outputted from the driver 116 is applied to only one input terminal of the memory under test 119, and that a response signal from one output terminal of the memory under test 119 is supplied to the comparator 117. However, the number of drivers 116 provided is actually equal to the number of input terminals of the memory under test 119, for example 512, and the number of comparators 117 provided is also equal to the number of output terminals of the memory under test 119 (since the number of input terminals provided is usually equal to the number of output terminals, the number of comparators 117 provided is equal to the number of drivers 116 provided). In addition, although the input terminals of the memory under test 119 are depicted, in FIG. 5, as separate terminals from the output terminals of the memory under test 119, there are many cases in general that each terminal of the memory under test 119 is used in common as both the input terminal and the output terminal. Moreover, although each of the elements (the main controller 111, the pattern generator 112, the timing generator 113, the waveform formatter 114, the logical comparator 115, the failure analysis memory 118, the failure relief analyzer 120, and the like) except the driver 116 and the comparator 117 is represented by one block, these elements except the main controller 111 and the timing generator 112 are also actually provided as many as the number of the drivers 116 (for example, 512). That is, only the main controller 111 and the timing generator 112 are used in common for the terminals of the memory under test 119.
FIG. 6 shows the internal structure of the memory under test 119. An IC memory constituted by a semiconductor integrated circuit has a plurality of storage areas 2 formed on the same semiconductor chip 1. Each storage area 2 is constituted by many memory cells aligned along row address lines and column address lines, and is called a memory cell array (MCA) in this technical field. A memory element having a desired storage capacity is constituted by these plural storage areas 2. In addition, each of the plurality of storage areas 2 is selectively accessed by a storage area (block) address signal that is to be described later on.
As shown in FIG. 7 in enlarged form, each storage area 2 has a memory cell array MCA in which memory cells have been arrayed in a matrix manner of rows and columns, and in addition to the memory cell array MCA, it is provided with a desired number of row spare lines SR and a desired number of column spare lines SC formed in the row address direction ROW and in the column address direction COL along the periphery of the memory cell array MCA, respectively. These spare lines SR and SC are provided for the purpose of repairing failure memory cells, and serve to change a memory under test that has been determined to be a defective or failure article to a non-defective or pass article by electrically replacing the detected failure memory cells in the storage area 2 with those spare lines. Further, in this example, a case is shown where two row spare lines SR are disposed along one side of the row address direction of the memory cell array MCA and two column spare lines SC are disposed along one side of the column address direction of the memory cell array MCA, respectively. However, it is needless to say that the number of spare lines and the positions where these spare lines are disposed are not limited to the example as illustrated.
Depending upon the number of the spare lines SR formed in the row address direction ROW and the number of spare lines SC formed in the column address direction COL, the number of failure memory cells that can be relieved by the spare lines provided in orthogonal direction to an address line in the storage area 2 is restricted. For this reason, after the testing has been completed, first of all, the number of failure memory cells is searched for each storage area 2, and row address lines and column address lines on which these failure memory cells are present are searched for each storage area 2, thereby to determine whether or not the failure memory cell or cells on the one address line can be relieved by the spare lines orthogonal to this one address line.
The failure relief analyzer 120 includes, as shown in FIG. 8, a row address failure number counter/memory RFC for counting and storing therein the number of failure memory cells present on each of the row address lines in each storage area 2, a column address failure number counter/memory CFC for counting and storing therein the number of failure memory cells present on each of the column address lines in each storage area 2, and a total failure number counter/memory TFC for counting and storing therein the total number of failure memory cells in each storage area 2. Further, the row address failure number counter/memory RFC and the column address failure number counter/memory CFC are constructed in practice such that these counters/memories RFC and CFC count the number of failure data read out from the failure analysis memory 118 each representing a failure memory cell on each of the row address lines and each of the column address lines, respectively, and the counted values are stored in their respective failure storing memories. The total failure number counter/memory TFC is constructed such that it accumulates, every time a failure data is read out from the failure analysis memory 118, the number of occurrences of failure data, and the accumulated value is stored in the total failure number storing memory of the total failure number counter/memory TFC.
As an occurrence state of failure memory cells, there is a case that, as shown in FIG. 9, many failure cells FC are present on one row address line RLN or on one column address line CLN and that the number of failure memory cells FC on one address line is larger than the number of spare lines SC or SR provided in the direction orthogonal to the address line RLN or CLN. Such state is generally called a must-repair MS in this technical field. This must-repair MS cannot be repaired by the spare lines SC or SR provided in the direction orthogonal to its address line RLN or CLN. Accordingly, it is necessary to relieve such a must-repair using a spare line SR or SC that is provided in parallel to the must-repair address line RLN or CNL. As a failure relief analyzing procedure, the must-repair MS must be first detected, and then, the spare line used for the repair of the must-repair MS and the repaired failure memory cells are excluded from the consideration for further failure relief, and thereafter it is determined whether or not the remaining failure memory cells can be relieved by the remaining spare lines.
A must-repair MS is searched in both the row address direction ROW and the column address direction COL. Specifically explaining, by reading out, first, the storage content of the row address failure number counter/memory RFC in sequence of the row addresses, the number of failure memory cells present on each of the row address lines of each storage area 2 can be read out. The number X1 of failure memory cells stored in each of the row addresses is compared with the number Y1 of the column spare lines SC. If the comparison result is X1 greater than Y1, that row address having the number X1 of failure memory cells is determined to be in must-repair state. The row address determined to be in must-repair state is sent to the main controller 111, and is stored therein as a row must-repair address.
Next, by reading out the storage content of the column address failure number counter/memory CFC in sequence of the column addresses, the number of failure memory cells present on each of the column address lines of each storage area 2 can be read out. The number X2 of failure memory cells stored in each of the column addresses is compared with the number Y2 of the row spare lines SR. If the comparison result is X2 greater than Y2, that column address having the number X2 of failure memory cells is determined to be in must-repair state. The column address determined to be in must-repair state is sent to the main controller 111, and is stored therein as a column must-repair address.
When the search operation of must-repair addresses has been completed, the main controller 111 sets the stored row and column must-repair addresses in the failure relief analyzer 120, and makes the failure relief analyzer 120 perform a data updating operation. A must-repair MS cannot be repaired unless one spare line that is in parallel with the must-repair address line is used. Therefore, if a must-repair MS is present only on one row address line RLN, for example, one row spare line SR must be used. As a result, if a must-repair MS is present only on one row address line RLN, there is performed an operation of decreasing the number of row spare lines SR by one as well as subtracting the number of failure memory cells on the row address line on which the must-repair MS is present from each of the row address failure number counter/memory RFC, column address failure number counter/memory CFC and the total failure number counter/memory TFC. By this operation, the row address line on which the must-repair has been present would have been repaired to a non-defective row address line.
Even if only one must-repair address is present on one of the row addresses, the number of the row spare lines SR is decreased by one, and hence the number of the row spare lines SR is changed. As a result, regarding the column address lines that are orthogonal to the row spare lines SR, a search operation for a must-repair must be performed again on the basis of the changed number of the row spare lines SR. The search condition in this case is to compare the number X2 of failure memory cells of each column address with a numerical value Y2xe2x88x921 resulting from the subtraction of one (1) from the number Y2 of the row spare lines SR. If the comparison result X2 greater than Y2xe2x88x921 is detected, that column address is sent to the main controller 111 as a column must-repair address, and is stored therein.
When the search operation of must-repair addresses in the column address direction COL has been completed, the main controller 111 sets again in the failure relief analyzer 120 the column must-repair address or addresses detected with respect to the column addresses, and makes the failure relief analyzer 120 perform a data updating operation. If a must-repair MS is present only on the column address line CLN, for example, this data updating operation is such that assuming that one column spare line SC has been used, the number of the column spare lines SC is subtracted by one (1), and further, the number of failure memory cells on the column address line on which the must-repair MS has been present is subtracted from each of the row address failure number counter/memory RFC, the column address failure number counter/memory CFC, and the total failure number counter/memory TFC. By this operation, the column address line on which the must-repair has been present would have been repaired to a non-defective column address line.
Since the number of the column spare lines SC is decreased by one by such updating operation, a search operation for a must-repair must be performed again this time with respect to the row address lines that are orthogonal to the column spare lines SC. In such manner, the search operation for a must-repair and the updating operation of the analysis data are repeated until any must-repair is not detected.
FIG. 10 shows an example in which a must-repair MS is present, for example, on an address line RLN having a row address RN in a storage area 2, the number of failure memory cells that compose the must-repair MS is, as illustrated, xe2x80x9c9xe2x80x9d, a failure memory cell FC is present in addition to this must-repair MS on each of other three row address lines as illustrated, two of these three failure memory cells FC are present on a column address line on which one of the failure memory cells of the must-repair MS is present, and remaining one failure memory cell FC is present on another column address line on which another one of the failure memory cells FC of the must-repair MS is present. In this case, a numerical value xe2x80x9c9xe2x80x9d is stored, as illustrated, in a row address RN of the row address failure number counter/memory RFC as the number of failure memory cells. A numerical value xe2x80x9c1xe2x80x9d is stored, as illustrated, in each of these other three row addresses of the row address failure number counter/memory RFC as the number of failure memory cells. On the other hand, as illustrated, numeric values xe2x80x9c3xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c1xe2x80x9d are stored in nine column addresses of the column address failure number counter/memory CFC, respectively.
As mentioned above, in order to relieve the must-repair MS on the row address line RLN, one of the row spare lines SR must be used. Therefore, if it is assumed that the must-repair MS in the row address RN is relieved using one of the spare lines SR, the numerical value stored in the row address RN of the row address failure number counter/memory RFC is decreased from xe2x80x9c9xe2x80x9d to xe2x80x9c0xe2x80x9d since the number of failure memory cells on the row address line is xe2x80x9c9xe2x80x9d. However, the numerical value xe2x80x9c1xe2x80x9d stored in each of the three other row addresses remains unchanged. Since each of the nine numerical values stored in each of all the nine column addresses of the column address failure number counter/memory CFC is decreased by one, those stored values become xe2x80x9c2xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c0xe2x80x9d, respectively. In addition, the numerical value stored in the total failure number counter/memory TFC is decreased from xe2x80x9c12xe2x80x9d to xe2x80x9c3xe2x80x9d.
The present invention relates to a method of analyzing a relief of failure cells in a memory that can locate in a short time addresses of remaining failure memory cells FC after the aforementioned relief processing of the must-repair MS is performed and a memory testing apparatus having a failure relief analyzer using this method.
In order to change a memory under test 119 to a non-defect article, all the failure memory cells whose failure data are stored in the failure analysis memory 118 must be relieved. Therefore, in a example shown in FIG. 10, it is necessary to relieve, using the spare lines SR and SC, all the failure memory cells FC remaining after the relief processing of the must-repair MS is performed. For this purpose, addresses of the failure memory cells FC remaining after the relief processing of the must-repair MS is performed must be located.
In the prior art system, the contents of the row address failure number counter/memory RFC are read out, under control of the main controller 111, in the sequential order in the row address direction ROW, and whenever the number of remaining failure memory cells is detected, the corresponding row address is stored in the main controller 111. In this manner, whether or not a failure memory cell is present is checked through the last row address. Similarly, the contents of the column address failure number counter/memory CFC are read out in the sequential order in the column address direction COL, and whenever the number of remaining failure memory cells is detected, the corresponding column address is stored in the main controller 111. In this manner, whether or not a failure memory cell is present is checked through the last column address.
When the searching operation of failure memory cells in the row address direction and the searching operation of failure memory cells in the column address direction are completed, the row addresses and the column addresses in which failure memory cells are present that have been temporarily stored in the main controller 111 are read out therefrom. A failure data of a failure memory cell FC is stored in the failure analysis memory 118, and each of a row address and a column address read out from the main controller 111 merely specifies only an address of an address line of the failure analysis memory 118 in which the failure memory cell FC is present. That is, each of a row address and a column address does not specify an address of the failure analysis memory 118 in which the failure memory cell FC is present. Therefore, since it is not possible to determine on which crossing point between a row address line and a column address line respectively corresponding to the read out row address and column address the failure memory cell FC is present, it is necessary to create addresses corresponding to all the crossing points to read out the contents of the failure analysis memory 118.
FIG. 11 shows, by a symbol xe2x80x9cxxe2x80x9d, crossing points produced by row address lines and column address lines respectively corresponding to the row addresses and column addresses at each of which a failure memory cell is present, the row and column addresses being read out from the main controller 111. Since crossing points on each of which a failure memory cell FC is present cannot be specified by only the read out addresses, in the prior art, the addresses corresponding to all of the illustrated crossing points are created, and the contents of the failure analysis memory 118 are read out with respect to these addresses to specify the addresses of the failure memory cells FC that actually exist, and thereafter the specified addresses are stored in the main controller 111. In reality, a failure memory cell FC is present on each of only the three crossing points each being shown by a symbol {circle around (X)}. Therefore, in the example shown in FIG. 11, unproductive or useless reading operations have been performed for a half (xc2xd) of six crossing points.
In this manner, in order to execute a relief analysis of failure memory cells still remaining after the process of relieving the must-repair MS has been performed, in the prior art, row addresses and column addresses at each of which at least one failure memory cell is present are previously detected under the control of the main controller 111 to store these addresses in the main controller 111. Then, these stored row addresses and column addresses are read out therefrom, and thereafter, the storage contents of the failure analysis memory 118 are read out from all of the addresses each having a possibility that a failure data of a failure memory cell may be present, and addresses at each of which a failure memory cell is really present are specified, thereby to store the specified addresses in the main controller 111. For this reason, the searching operation for address lines where failure memory cells remain, i.e., reading of the row address failure number counter/memory RFC and the column address failure number counter/memory CFC, formatting of the addresses where failure memory cells may be present, and reading of the failure analysis memory 118 must be repeatedly done many times. Accordingly, there is a drawback in the prior art that the efficiency is very low, and it takes a long time to search addresses of failure memory cells.
In recent years, there has been a tendency that the storage capacity of a memory under test is increasing, and the number of storage areas to be relieved and the area of each of the storage areas are increased. Therefore, the searching time of the addresses of failure memory cells still remaining after completion of the relief operation of a must-repair has been increased more and more, which results in a great obstacle to a quick or high-speed processing of a failure relief analysis for a memory. In addition, in this manner, a long time is needed to perform a processing of the relief analysis of failure memory cells, resulting in a problem that the testing time of an IC memory is made long as a whole.
It is a first object of the present invention to provide a method of analyzing a relief of failure cells in a memory, which is capable of completing a failure relief analysis in a short time even if a memory under test has many storage areas.
It is a second object of the present invention to provide a memory testing apparatus having a failure relief analyzer using the above method of analyzing a relief of failure cells.
It is a third object of the present invention to provide a method of analyzing a relief of failure cells in a memory, which is capable of searching and detecting in a short time an address of a failure memory cell remaining in a memory after a process for relieving a must-repair has been completed.
It is a fourth object of the present invention to provide a memory testing apparatus having a failure relief analyzer using the method of analyzing a relief of failure cells described in the above third object of the present invention.
In order to accomplish the aforesaid objects, there is provided, in one aspect of the present invention, a method of analyzing a repair of failure cell in a memory comprising the steps of: testing a memory having a plurality of storage areas selectively accessed to carry out a reading operation and a writing operation; and detecting the number of failure memory cells and addresses thereof resulting from the test result to analyze whether the memory under test can be relieved or not, and further comprising the steps of: searching each of the plural storage areas to determine whether any failure memory cell is present in each storage area or not; searching, each time a failure memory cell is detected, a row address or column address of the detected failure memory cell on the storage area from which the failure memory cell has been detected; detecting, each time a row address or column address of the detected failure memory cell is detected, a column address or row address of the detected failure memory cell on the detected row address line or column address line, thereby to specify an address of the detected failure memory cell; and storing the specified address of the detected failure memory cell.
In another aspect of the present invention, there is provided a memory testing apparatus provided with a failure relief analyzer and for testing a memory having a plurality of storage areas, the failure relief analyzer comprising: an analyzed storage area detector for searching whether a failure memory cell exists or not on each of plural storage areas of a memory under test and determining whether a failure relief analysis should be performed or not for each storage area; a failure line searching apparatus for detecting, in the storage area where said analyzed storage area detector has determined that a failure relief analysis should be performed, row addresses or column addresses to detect whether a failure memory cell exists or not; an address scanning apparatus started when the failure line searching apparatus detects a row address line or column address line where a failure memory cell exists, and detecting an address in the direction orthogonal to the row address line or column address line on which the detected failure memory cell exists; and a failure cell address memory for storing the address of the failure memory cell detected by the failure line searching apparatus and the address scanning apparatus.
In a preferred embodiment, the aforesaid analyzed storage area detector of the failure relief analyzer comprises: a storage area address generator for generating addresses given respectively to said plurality of storage areas constituting the memory under test; a total failure number counter/memory accessed by storage area address signals outputted from the storage area address generator and for storing the total number of failure memory cells for each storage area; zero detector for detecting the fact that the total number of failure memory cells read out of said total failure number counter/memory is xe2x80x9c0xe2x80x9d or a numerical value other than xe2x80x9c0xe2x80x9d.
The aforesaid failure line searching apparatus of the failure relief analyzer comprises: a row address generator or column address generator for generating row addresses or column addresses on each of the storage areas; a row address failure number counter/memory or column address failure number counter/memory for storing the number of failure memory cells on each row address line or each column address line for each storage area; zero detector for detecting whether the number of failure memory cells read out of either one of the row address failure number counter/memory or column address failure number counter/memory is xe2x80x9c0xe2x80x9d or a numerical value other than xe2x80x9c0xe2x80x9d; and means of starting the operation of the address scanning apparatus each time the zero detector detects a numerical value other than xe2x80x9c0xe2x80x9d.
The aforesaid address scanning apparatus of the failure relief analyzer comprises: a column address generator or row address generator for generating column addresses or row addresses on each of the storage areas; a column address failure number counter/memory or row address failure number counter/memory for storing the number of failure memory cells on each column address line or each row address line for each storage area; zero detector for detecting whether the number of failure memory cells read out of either one of the column address failure number counter/memory or row address failure number counter/memory is xe2x80x9c0xe2x80x9d or a numerical value other than xe2x80x9c0xe2x80x9d; and writing control means for causing addresses to be stored in the failure cell address memory, the addresses being specified by address signals generated respectively from the storage area address generator, the row address generator and the column address generator, each time the zero detector detects a numerical value other than xe2x80x9c0xe2x80x9d and at the same time a read-out data of a failure analysis memory provided in the memory testing apparatus is xe2x80x9cfailxe2x80x9d.
According to the method of analyzing a relief of failure cells in a memory and the memory testing apparatus having a failure relief analyzer using this method, a row address or a column address at which a failure memory cell is present is detected by a failure line searching apparatus. When a row address or a column address at which a failure memory cell is present is detected, addresses (column addresses or row addresses) in the orthogonal direction to the row address line or column address line are immediately searched at that address position by an address scanning apparatus, and at the same time, the content of the failure analysis memory is read out, thereby to specify an address of the detected failure memory cell.
When an address of the failure memory cell is specified with respect to its row address and its column address, that address is stored in a memory, and the failure line searching apparatus is re-started to operate, thereby to continue the searching operation for a failure cell. When the failure cell searching operation reaches the last row address or column address, the failure relief analysis of that storage area is completed, and the object to be analyzed is moved to the failure relief analysis of the next storage area.
In this manner, when the failure line searching apparatus detects the presence of a failure memory cell, a search for addresses in the orthogonal direction is immediately executed at that address position so that an address of the detected failure memory cell is specified. As a result, there is no need to perform such operation that the address where a failure memory cell is detected is once set, and that the stored addresses are read out after all of the searching operation for failure memory cells have been completed to specify an address of each of the failure memory cells as in the prior art. Accordingly, an address of a failure memory cell can be specified in a short time, resulting in that the time period required for a failure relief analysis can be considerably decreased.